# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# Power and configuration pins
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208-P.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208-P.txt XC3S500E-PQ208-P.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
#
10		pwr	line	r		GND	GND	GND
17		pwr	line	r		GND	GND	GND
27		pwr	line	r		GND	GND	GND
37		pwr	line	r		GND	GND	GND
52		pwr	line	r		GND	GND	GND
53		pwr	line	r		GND	GND	GND
70		pwr	line	r		GND	GND	GND
79		pwr	line	r		GND	GND	GND
85		pwr	line	r		GND	GND	GND
95		pwr	line	r		GND	GND	GND
105		pwr	line	r		GND	GND	GND
121		pwr	line	r		GND	GND	GND
131		pwr	line	r		GND	GND	GND
141		pwr	line	r		GND	GND	GND
156		pwr	line	r		GND	GND	GND
173		pwr	line	r		GND	GND	GND
182		pwr	line	r		GND	GND	GND
188		pwr	line	r		GND	GND	GND
198		pwr	line	r		GND	GND	GND
208		pwr	line	r		GND	GND	GND
#
7		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
44		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
66		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
92		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
111		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
149		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
166		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
195		pwr	line	r		VCCAUX	VCCAUX	VCCAUX
#
13		pwr	line	r		VCCINT	VCCINT	VCCINT
67		pwr	line	r		VCCINT	VCCINT	VCCINT
117		pwr	line	r		VCCINT	VCCINT	VCCINT
170		pwr	line	r		VCCINT	VCCINT	VCCINT
#
176		pwr	line	l		VCCO_0	VCCO	0
191		pwr	line	l		VCCO_0	VCCO	0
201		pwr	line	l		VCCO_0	VCCO	0
#
114		pwr	line	l		VCCO_1	VCCO	1
125		pwr	line	l		VCCO_1	VCCO	1
143		pwr	line	l		VCCO_1	VCCO	1
#
59		pwr	line	l		VCCO_2	VCCO	2
73		pwr	line	l		VCCO_2	VCCO	2
88		pwr	line	l		VCCO_2	VCCO	2
#
21		pwr	line	l		VCCO_3	VCCO	3
38		pwr	line	l		VCCO_3	VCCO	3
46		pwr	line	l		VCCO_3	VCCO	3
#
1		io	line	l		PROG_B	CONFIG	VCCAUX
104		io	line	l		DONE	CONFIG	VCCAUX
155		io	line	l		TMS	JTAG	VCCAUX
157		io	line	l		TDO	JTAG	VCCAUX
158		io	line	l		TCK	JTAG	VCCAUX
207		io	line	l		TDI	JTAG	VCCAUX

