# Symbol definition of Spartan-3E FPGA for gschem/gEDA
# Bank 0 (_0 deleted in pinlabel)
# S. Salewski, 26-OCT-2007
# File: XC3S500E-PQ208-B0.txt (based on file pq208_pinout.csv available from Xilinx)
# The Python script "tragesym" is used to convert this textual symbol definition into a symbol
# usage: tragesym XC3S500E-PQ208-B0.txt XC3S500E-PQ208-B0.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=2400
pinwidthvertical=200
pinwidthhorizontal=400

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=XC3S500E-PQ208
device=XC3S500E-PQ208
refdes=U?
footprint=QFP208_28
description=FPGA
documentation=http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	comment
#-----------------------------------------------------
#pinnr	seq	type	style	posit	net 	label	type	bank		
159		in	line	l		IP	INPUT	0
160		io	line	l		IO_L01P	I/O	0
161		io	line	l		IO_L01N	I/O	0
162		io	line	l		IO_L02P	I/O	0
163		io	line	l		IO_L02N/VREF	VREF	0
164		io	line	l		IO_L03P	I/O	0
165		io	line	l		IO_L03N	I/O	0
167		io	line	l		IO_L04P	I/O	0
168		io	line	l		IO_L04N/VREF	VREF	0
169		in	line	l		IP	INPUT	0
171		io	line	l		IO_L05P	I/O	0
172		io	line	l		IO_L05N	I/O	0
174		in	line	l		IP_L06P	INPUT	0
175		in	line	l		IP_L06N	INPUT	0
177		io	line	l		IO_L07P/GCLK4	GCLK	0
178		io	line	l		IO_L07N/GCLK5	GCLK	0
179		io	line	l		IO/VREF	VREF	0
180		io	line	l		IO_L08P/GCLK6	GCLK	0
181		io	line	l		IO_L08N/GCLK7	GCLK	0
183		in	line	l		IP_L09P/GCLK8	GCLK	0
184		in	line	l		IP_L09N/GCLK9	GCLK	0
185		io	line	l		IO_L10P/GCLK10	GCLK	0
186		io	line	l		IO_L10N/GCLK11	GCLK	0
187		io	line	l		IO	I/O	0
189		io	line	l		IO_L11P	I/O	0
190		io	line	l		IO_L11N	I/O	0
192		io	line	l		IO_L12P	I/O	0
193		io	line	l		IO_L12N/VREF	VREF	0
194		in	line	l		IP	INPUT	0
196		io	line	l		IO_L13P	I/O	0
197		io	line	l		IO_L13N	I/O	0
199		io	line	l		IO_L14P	I/O	0
200		io	line	l		IO_L14N/VREF	VREF	0
202		io	line	l		IO_L15P	I/O	0
203		io	line	l		IO_L15N	I/O	0
204		in	line	l		IP	INPUT	0
205		io	line	l		IO_L16P	I/O	0
206		io	line	l		IO_L16N/HSWAP	DUAL	0
#

