# Symbol definition of TPIC6595 (DIP20 and SO20 footprint) for gschem/gEDA
# S. Salewski, 08-APR-2008
# File: TPIC6595-2.txt
# The Python script "tragesym" is used to convert this textual symbol definition to a symbol
# usage: tragesym TPIC6595-2.txt TPIC6595-2.sym

# tragesym options

[options]
# wordswap swaps labels if the pin is on the right side and looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=no
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=1600
pinwidthvertical=300
pinwidthhorizontal=300

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20060113 1
name=TPIC6595
device=TPIC6595
refdes=U?
footprint=SO20
description=Power Logic 8-Bit Shift Register
documentation=http://focus.ti.com/docs/prod/folders/print/tpic6595.html
author=Stefan Salewski
dist-license=GPL
use-license=unlimited
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
comment=generated with Python script tragesym

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label
#-----------------------------------------------------
1		pwr	line	b		PGND
2		pwr	line	t		VCC
3		in	line	l		SERIN
4		out	line	r		DRAIN0
5		out	line	r		DRAIN1
6		out	line	r		DRAIN2
7		out	line	r		DRAIN3
8		in	line	l		\_SRCLR
9		in	line	l		\_G
10		pwr	line	b		PGND
20		pwr	line	b		PGND
19		pwr	line	b		LGND
18		out	line	l		SEROUT
17		out	line	r		DRAIN7
16		out	line	r		DRAIN76
15		out	line	r		DRAIN5
14		out	line	r		DRAIN4
13		in	line	l		SRCK
12		in	line	l		RCK
11		pwr	line	b		PGND

